The present invention relates generally to data transmission paths for integrated circuit devices and, more particularly, to a system and method for implementing self-timed, decoded data paths for input/outputs systems in integrated circuits.
Digital data paths for wide input/output (I/O) circuits and macros in integrated circuit devices typically consume the largest percentage of power within the macro and are often in the critical performance path. This in turn drives a desire to reduce the power consumption of the data path while maintaining the same performance level. In order to properly size power supplies for such wide I/O devices, “worst case” data patterns are assumed. In the context of digital data I/O devices, this worst case is represented by the data for each path changing on each clock cycle, since this results in charging/discharging of the data lines that define each data path.
Relatively speaking, single ended static systems (i.e., those systems in which only the true value of the digital bit, and not the complement thereof, is transmitted on a data line, and which line is not precharged to a defined value) consume the least amount of worst case power for full rail designs, because power is only consumed every other clock cycle. However, with a single ended data bus (either static or dynamic), the latching of the received data is not “self-timed” because the complementary bit is not transmitted to the receiving latch, and thus the data capture is dependent upon a global strobe (i.e., system clock). This is also the case for a single ended dynamic system, where a single true leg is pre-charged to a logic “1” state and discharged only when transmitting a logic “0” state. Self-timing cannot be performed because a transition is not guaranteed on each data bit independent of its state. Other low power data paths utilize small signal swing data lines with local amplification, but again this comes at the expense of performance, complexity and potential noise issues.
On the other hand, dynamic precharge schemes utilize data lines for both the true bit and its complement. In operation, the true/complement data line pairs are precharged to a known state, and one is thereafter discharged during data transmission. This configuration offers better performance as a result of the self-timing capability, given that the dual lines provide either a set or a reset signal to the capture latch. Therefore, the time lost in using a global strobe or clock that must satisfy reasonable data setup times to the capture latch is removed. The capture latch will transition to the new data state as soon as the data is available. Conversely, this scheme consumes twice the power of the single ended static system, since one data line always switches during each cycle in the worst case power consumption scenario.
Accordingly, it would be desirable to be able to minimize the power consumption of such data lines while still providing the benefits of self-timing.